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lt3796 1 3796f typical application features description 100v constant-current and constant-voltage controller with dual current sense the lt ? 3796 is a dc/dc controller designed to regulate a constant-current or constant-voltage and is ideal for driv- ing leds. it drives a low side external n-channel power mosfet from an internal regulated 7.7v supply. the fixed frequency and current mode architecture result in stable operation over a wide range of supply and output volt - ages. two ground referred voltage fb pins serve as the input for several led protection features, and also allow the converter to operate as a constant-voltage source. the lt3796 features a programmable threshold output sense amplifier with rail-to-rail common mode range. the lt3796 also includes a separate high side current sensing amplifier that is gain configurable with two resistors. the tg pin inverts and level shifts the pwm signal to drive the gate of the external pmos. the pwm input provides led dimming ratios of up to 3000:1, and the ctrl input provides additional analog dimming capability. boost led driver with input current monitor applications n 3000:1 true color pwm? dimming n wide input voltage range: 6v to 100v n current monitoring up to 100v n high side pmos disconnect and pwm switch driver n constant-current and constant-voltage regulation n dual current sense amplifiers with reporting n c/10 detection for battery and supercap charging n linear current sense threshold programming n short-circuit protection n adjustable frequency: 100khz to 1mhz n frequency synchronization n programmable open led protection with vmode flag n programmable undervoltage lockout with hysteresis n soft-start with programmable fault restart timer n low shutdown current: <1a n available in 28-lead tssop package n high power led, high voltage led n battery and supercap chargers n accurate current limited voltage regulators l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7199560, 7321203, 7746300. efficiency vs v in v in (v) 0 90 100 30 50 3796 ta01b 85 80 10 20 40 60 75 70 95 efficiency (%) 118k cspv s csn rt v c vmode fault vmode fault 2k 85v led 400ma lt3796 3796 ta01a ctrl csout pwm ismon pwm sync ss fb2 en/uvlo v ref gnd fb1 isp isn tg intv cc gate sense 10nf 22h 50m v in 9v to 60v 100v (transient) 4.7f 31.6k 250khz 10k v in intv cc 499k 97.6k 1m 2.2f 4 13.7k 15m 620m 40.2k 10nf 100k 100k c sout intv cc 2.2f 3 1m 0.1f 0.1f
lt3796 2 3796f pin configuration absolute maximum ratings v in , v s .................................................................... 100v en/uvlo ................................................................. 100v isp, isn ................................................................... 100v tg, gate ............................................................... note 3 csp, csn ................................................................ 100v v s - c s p, v s - csn ....................................... C0.3v to 4v intv cc (note 2) ..................................... 8.6v, v in + 0.3v pwm, vmode , fa u lt ............................................... 12v fb1, fb2, sync ........................................................... 8v ctrl ......................................................................... 15v sense ...................................................................... 0.5v ismon, csout ........................................................... 5v v c , v ref , ss ................................................................ 3v rt ............................................................................... 2v operating junction temperature range (note 4) lt3796e/lt3796i .................................. C40 to 125c lt3796h ................................................ C40 to 150c storage temperature range ...................... C65 to 150c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 isp isn tg gnd ismon fb2 fb1 v c ctrl v ref ss rt sync pwm csout csp csn v s en/uvlo v in gnd gnd intv cc gate sense gnd vmode fault 29 gnd t jmax = 150c, ja = 30c/w, jc = 10c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3796efe#pbf lt3796efe#trpbf lt3796fe 28-lead plastic tssop C40c to 125c lt3796ife#pbf lt3796ife#trpbf lt3796fe 28-lead plastic tssop C40c to 125c lt3796hfe#pbf lt3796hfe#trpbf lt3796fe 28-lead plastic tssop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
lt3796 3 3796f electrical characteristics parameter conditions min typ max units v in minimum operating voltage v in tied to intv cc 6 v v in shutdown i q en/uvlo = 0v, pwm = 0v en/uvlo = 1.15v, pwm = 0v 1 12 a a v in operating i q (not switching) r t = 82.5k to gnd, fb1 = 1.5v 2.5 3 ma v ref voltage C100a i ref 10a l 1.97 2.015 2.06 v v ref pin line regulation 6v < v in < 100v 1.5 m%/v v ref pin load regulation C100a < i ref < 0a 10 m%/a sense current limit threshold l 100 113 125 mv sense input bias current current out of pin 60 a ss sourcing current ss = 0v 28 a ss sinking current isp C isn = 1v, ss = 2v 2.8 a error amplifier full scale led current sense threshold (v (isp-isn) ) isp = 48v, ctrl 1.2v isp = 0v, ctrl 1.2v l l 243 243 250 250 257 257 mv mv 9/10th led current sense threshold (v (isp-isn) ) ctrl = 1v, isp = 48v ctrl = 1v, isp = 0v l l 220 220 225 225 230 230 mv mv 1/2 led current sense threshold (v (isp-isn) ) ctrl = 0.6v, isp = 48v ctrl = 0.6v, isp = 0v l l 119 119 125 125 131 131 mv mv 1/10th led current sense threshold (v (isp-isn) ) ctrl = 0.2v, isp = 48v ctrl = 0.2v, isp = 0v l l 16 16 25 25 32 32 mv mv isp/isn current monitor voltage (v ismon ) v (isp-isn) = 250mv, isp = 48v, C50a < i ismon < 0 a v (isp-isn) = 250mv, isp = 0v, C50a < i ismon < 0 a l l 0.96 0.96 1 1 1.04 1.04 v v isp/isn over current protection threshold (v (isp-isn) ) isn = 48v isn = 0v l l 360 360 375 375 390 390 mv mv ctrl input bias current current out of pin, ctrl = 1.2v 50 200 na isp/isn current sense amplifier input common mode range 0 100 v isp/isn input current bias current (combined) pwm = 5v (active), isp = 48v pwm = 0v (standby), isp = 48v 700 0 0.1 a a isp/isn current sense amplifier g m v (isp-isn) = 250mv 400 s v c output impedance 2000 k v c standby input bias current pwm = 0v C20 20 na fb1, fb2 regulation voltage (v fb ) isp = isn = 48v isp = isn = 48v l 1.230 1.238 1.250 1.250 1.270 1.264 v v fb1 amplifier g m 800 1000 1200 s fb2 amplifier g m 130 170 210 s fb1, fb2 pin input bias current fb = v fb 100 200 na fb1 open led threshold vmode falling, isp = isn = 48v v fb C 70mv v fb C 60mv v fb C 50mv v c/10 comparator threshold (v (isp-isn) ) vmode falling, fb1 = 1.5v, isp = 48v vmode falling, fb1 = 1.5v, isn = 0v 25 25 mv mv fb1 overvoltage threshold fault falling v fb + 35mv v fb + 50mv v fb + 60mv v fb2 overvoltage threshold tg rising v fb + 35mv v fb + 50mv v fb + 60mv v v c current mode gain (?v vc /?v sense ) 4.2 v/v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted.
lt3796 4 3796f parameter conditions min typ max units current sense amplifier (csa) power supply voltage range (v s ) l 3 100 v csa input voltage common mode range (v csp and v csn ) l 2.5 100 v csout maximum output current csout = 10k to gnd l 200 a input voltage offset ( v (csp-csn) ) v sns = 100mv, v s = 48v (note 5) l C3 0 3 mv csp, csn input bias current v sns = 0mv, r in1 = r in2 = 1k (note 5) 100 na csp, csn input current offset v sns = 0mv, r in1 = r in2 = 1k (note 5) 0 na v s supply current v s = 48v 80 a input step response ( to 50% of output step) ?v sense = 100mv step, r in1 = r in2 = 1k, r out = 10k 1 s linear regulator intv cc regulation voltage l 7.4 7.7 8 v dropout (v in C intv cc ) i intvcc = C20ma, v in = 6v 400 mv intv cc current limit v in = 100v, intv cc = 6v v in = 12v, intv cc = 6v 20 85 ma ma intv cc shutdown bias current if externally driven to 7v en/uvlo = 0v, intv cc = 7v 10 a intv cc undervoltage lockout 3.8 4 4.1 v intv cc undervoltage lockout hysteresis 150 mv oscillator switching frequency r t = 82.5k r t = 19.6k r t = 6.65k l l l 85 340 900 105 400 1000 125 480 1150 khz khz khz minimum off-time (note 6) 190 ns minimum on-time (note 6) 210 ns logic input/outputs pwm input threshold rising l 0.96 1 1.04 v pwm pin bias current 10 a en/uvlo threshold voltage falling l 1.185 1.220 1.250 v en/uvlo rising hysteresis 20 mv en/uvlo input low voltage i vin drops below 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v 2.5 3 3.8 a en/uvlo pin bias current high en/uvlo = 1.30v 40 200 na vmode output low i vmode = 0.5ma 300 mv fault output low i fault = 0.5ma 300 mv sync pin resistance to gnd 40 k sync input low threshold 0.4 v sync input high threshold 1.5 v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted.
lt3796 5 3796f parameter conditions min typ max units gate driver t r nmos gate driver output rise time c l = 3300pf, 10% to 90% 20 ns t f nmos gate driver output fall time c l = 3300pf, 10% to 90% 18 ns nmos gate output low (v ol ) 0.05 v nmos gate output high (v oh ) intv cc C 0.05 v t r top gate driver output rise time c l = 300pf 50 ns t f top gate driver output fall time c l = 300pf 100 ns top gate on voltage (v isp -v tg ) isp = 48v 7 8 v top gate off voltage (v isp -v tg ) pwm = 0v, isp = 48v 0 0.3 v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, en/uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: operating maximum for intv cc is 8v. note 3: do not apply a positive or negative voltage source to tg and gate pins, otherwise permanent damage may occur. note 4: the lt3796e is guaranteed to meet specified performance from 0c to 125c. specifications over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the lt3796i is guaranteed to meet performance specifications over the C40c to 125c operating temperature range. the lt3796h is guaranteed over the full C40c to 150 c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 5: measured in servo. see figure 9 for details. note 6: see duty cycle considerations in the applications information section.
lt3796 6 3796f isp/isn input bias current vs v isp ,v isn v ref voltage vs temperature isp/isn overcurrent protection threshold vs temperature typical performance characteristics v (isp-isn) threshold vs fb voltage v fb vs temperature v (isp-isn) threshold vs v ctrl v (isp-isn) threshold vs v isp v (isp-isn) full-scale threshold vs temperature t a = 25c, unless otherwise noted. v (isp-isn) threshold at ctrl = 0.6v vs temperature temperature (c) ?50 250 254 25 75 3796 g03 249 248 ?25 0 50 100 150125 247 246 253 252 251 v (isp-isn) threshold (mv) isp = 48v ctrl = 2v temperature (c) ?50 128 3796 g03a ?25 0 25 50 75 100 150125 127 125 124 126 122 123 v (isp-isn) (mv) v isp (v) 0 251 253 40 80 3796 g02 250 249 20 60 100 248 247 252 v (isp-isn) threshold (mv) temperature (c) ?50 1.24 1.27 3796 g05 ?25 0 25 50 10075 150125 1.23 1.26 1.25 v fb (v) temperature (c) ?50 374 372 380 3796 g06 ?25 0 25 50 10075 150125 370 378 376 isp/isn overcurrent threshold (mv) v isp , v isn (v) 0 500 3796 g07 20 40 60 100 80 400 300 200 100 0 800 900 700 600 isp, isn bias current (a) isp isn pwm = 5v v fb (v) 1.1 150 300 fb1 3796 g04 100 1.15 1.2 1.25 1.3 50 0 250 200 v (isp-isn) threshold (mv) fb2 temperature (c) ?50 2.01 2.00 2.05 3796 g08 ?25 0 25 50 10075 125 150 1.99 1.98 1.97 1.96 2.04 2.03 2.02 v ref (v) i ref = 0a i ref = ?100a v ctrl (v) 0 200 300 0.6 1.0 3796 g01 150 100 0.2 0.4 0.8 1.2 1.4 50 0 250 v (isp-isn) threshold (mv)
lt3796 7 3796f typical performance characteristics r t vs switching frequency switching frequency vs temperature quiescent current vs v in v ismon vs v (isp-isn) en/uvlo hysteresis current vs temperature v ref vs v in t a = 25c, unless otherwise noted. v (isp-isn) (mv) 0 1200 1000 1400 2000 3796 g13 100 200 300 400 500 800 600 400 200 0 1600 1800 v ismon (mv) temperature (c) ?50 400 390 410 440 3796 g11 0?25 25 50 75 100 150125 380 370 360 420 430 switching frequency (khz) r t = 19.6k en/uvlo falling/rising threshold vs temperature sense current limit threshold vs temperature temperature (c) ?50 1.25 1.24 1.28 3796 g15 ?25 0 25 50 75 100 150125 1.23 1.22 1.21 1.20 1.19 1.26 1.27 en/uvlo (v) en/uvlo rising threshold en/uvlo falling threshold temperature (c) ?50 115 114 118 3796 g16 ?25 0 25 50 75 100 125 150 113 112 111 110 109 108 116 117 sense threshold (mv) switching frequency (khz) 0 3796 g10 400300200100 500 600 700 800 900 1000 100 10 1 r t (k) temperature (c) ?50 2.0 1.5 3.5 3796 g14 ?25 0 25 50 75 100 150125 1.0 0.5 0 2.5 3.0 en/uvlo hysteresis current (a) switching frequency vs ss voltage ss voltage (mv) 0 450 3796 g11a 200 400 600 800 1000 1200 350 400 250 200 300 150 0 50 100 sw frequency (khz) v in (v) 0 2.01 2.00 2.02 2.05 3796 g09 4020 60 80 100 1.99 1.98 1.97 2.03 2.04 v ref (v) i ref = 0a v in (v) 0 1.0 1.5 2.5 3796 g12 4020 60 80 100 0.5 0 2.0 v in current (ma) pwm = 0v
lt3796 8 3796f intv cc current limit vs temperature intv cc vs v in intv cc dropout voltage vs current, temperature intv cc vs temperature v (csp-csn) offset voltage with different i csout vs v s intv cc current limit vs v in typical performance characteristics t a = 25c, unless otherwise noted. temperature (c) ?50 70 80 100 3796 g19 0?25 25 50 75 150 100 125 60 50 90 intv cc current limit (ma) v in = 24v v in = 48v current sense amplifier gain error vs temperature v (csp-csn) offset voltage vs temperature temperature (c) ?50 0.6 3796 g24 ?25 0 25 50 75 100 125 150 0.4 0.2 0 ?0.2 v (csp-csn) (mv) i csout = 10a i csout = 100a i csout = 50a temperature (c) ?50 2.0 3796 g25 ?25 0 25 50 75 100 125 150 1.0 1.5 0 ?0.5 0.5 ?1.0 ?2 ?1.5 gain error (%) i csout = 10a i csout = 100a i csout = 50a intv cc load (ma) 0 1800 v in = 6v 3796 g21 5 10 15 20 125c 25c ?55c 1600 1400 1200 1000 800 600 400 200 0 intv cc dropout (mv) 150c 75c 0c ?40c v in (v) 0 40 60 120 3796 g18 4020 60 80 100 20 0 80 100 intv cc current limit (ma) v in (v) 0 9 3796 g20 20 40 60 80 100 7 8 6 5 4 3 2 1 0 intv cc (v) temperature (c) ?50 3796 g22 ?25 0 5025 75 125100 150 7.9 8.0 7.8 7.7 7.6 7.5 7.4 7.3 intv cc (v) sense current limit threshold vs duty cycle duty cycle (%) 0 120 115 3796 g17 20 40 60 80 100 110 105 100 sense threshold (mv) v s (v) 0 2 3796 g23 20 40 60 80 100 1 0 ?1 ?2 v (csp-csn) (mv) i csout = 100a i csout = 10a see note 5 for test setup i csout = 50a
lt3796 9 3796f top gate (pmos) rise/fall time vs capacitance current sense amplifier gain vs frequency nmos gate rise/fall time vs capacitance typical performance characteristics top gate driver rising edge top gate driver falling edge capacitance (nf) 0 160 3796 g27 10 20 30 40 50 120 140 80 60 100 40 0 20 time (ns) rise time fall time capacitance (nf) 0 800 3796 g28 1 2 3 4 5 6 7 8 9 10 600 700 400 300 500 200 0 100 time (ns) fall time rise time frequency (khz) 0.01 30 3796 g26 0.1 1 10 100 1000 10000 20 25 10 5 0 15 ?5 ?20 ?10 ?15 gain (db) v s = 48v, r in = 1k r out = 10k, v sense = 100mv (note 5) pmos vishay siliconix si7113dn 3796 g29 100ns/div 5v pwm tg 0v 85v 75v pmos vishay siliconix si7113dn 3796 g30 100ns/div 5v pwm tg 0v 85v 75v t a = 25c, unless otherwise noted.
lt3796 10 3796f pin functions isp (pin 1): connection point for the positive terminal of the current feedback resistor (r led ). also serves as positive rail for tg pin driver. isn (pin 2): connection point for the negative terminal of the current feedback resistor (r led ). tg (pin 3): top gate driver output. an inverted pwm signal drives series pmos device between v isp and (v isp C 7v) if v isp > 7v. an internal 7v clamp protects the pmos gate by limiting vgs. leave tg unconnected if not used. gnd (pins 4, 17, 21, 22, exposed pad pin 29): ground. these pins also serve as current sense input for control loop, sensing negative terminal of current sense resistor in the source of the n-channel mosfet. solder the exposed pad directly to ground plane. ismon (pin 5): isp/isn current report pin. the led current sensed by isp/isn inputs is reported as v ismon = i led ? r led ? 4. leave ismon pin unconnected if not used. when pwm is low, ismon is driven to ground. bypass with a 47nf capacitor or higher if needed. fb2 (pin 6): voltage loop feedback 2 pin. this pin is connected to the internal transconductance amplifier posi - tive input node. the internal transconductance amplifier with output v c regulates fb2 to 1.25v through the dc/ dc converter. if fb2 is driven above 1.3v, the tg pin is pulled high to turn off the external pmos and gate pin is driven to gnd to turn off the external n-channel mosfet. connect to gnd if not used. fb1 (pin 7): voltage loop feedback 1 pin. fb1 is intended for constant-voltage regulation or for led protection/open led detection. the internal transconductance amplifier with output v c regulates fb1 to 1.25v (nominal) through the dc/dc converter. if the fb1 input is regulating the loop and v (isp-isn) is less than 25mv (normal), the vmode pull-down is asserted. this action may signal an open led fault. if fb1 is driven above the 1.3v (by an external power supply spike, for example), the fault pull-down is asserted, the gate pin is pulled low to turn off the external n-channel mosfet and the tg pin is driven high to protect the leds from an overcurrent event. do not leave the fb1 pin open. if not used, connect fb1 to gnd. v c (pin 8): transconductance error amplifier output pin. used to stabilize the control loop with an rc network. this pin is high impedance when pwm is low, a feature that stores the demand current state variable for the next pwm high transition. connect a capacitor between this pin and gnd; a resistor in series with the capacitor is recommended for fast transient response. do not leave this pin open. ctrl (pin 9): current sense threshold adjustment pin. regulating threshold v (isp-isn) is 0.25 ? v ctrl plus an offset for 0.1v < v ctrl < 1v. for v ctrl > 1.2v the current sense threshold is constant at the full-scale value of 250mv. for 1v < v ctrl < 1.2v, the dependence of the current sense threshold upon v ctrl transitions from a linear function to a constant value, reaching 98% of full-scale value by v ctrl = 1.1v. connect ctrl to v ref for the 250mv default current threshold. do not leave this pin open. pull ctrl pin to gnd for zero led current. v ref (pin 10): voltage reference output pin. typically 2.015v. this pin drives a resistor divider for the ctrl pin, either for analog dimming or for temperature limit/ compensation of led load. it can supply up to 100a. ss (pin 11): soft-start pin. this pin modulates oscillator frequency and compensation pin voltage (v c ) clamp. the soft-start interval is set with an external capacitor. the pin has a 28a (typical) pull-up current source to an internal 2.5v rail. this pin can be used as fault timer. provided the ss pin has exceeded 1.7v, the pull-up current source is disabled and a 2.8a pull-down current enabled when any one of the following fault conditions happen: 1. led overcurrent 2. intv cc undervoltage 3. thermal limit the ss pin must be discharged below 0.2v to reinitiate a soft-start cycle. switching is disabled until ss is recharged. rt (pin 12): switching frequency adjustment pin. set the frequency using a resistor to gnd (for resistor values, see the typical performance curve or table 2). do not leave the rt pin open.
lt3796 11 3796f pin functions sync (pin 13): the sync pin is used to synchronize the internal oscillator to an external logic level signal. if sync is used, the r t resistor should be chosen to program an internal switching frequency 20% slower than the sync pulse frequency. gate turn-on occurs a fixed delay after the rising edge of sync. use a 50% duty cycle waveform to drive this pin. if not used, tie this pin to gnd. pwm (pin 14): pwm input signal pin. a signal low turns off switching, idles the oscillator, disconnects the v c pin from all internal loads, and makes the tg pin high. fault (pin 15): an open-collector pull-down on fault asserts when any of the following conditions happen: 1. fb1 overvoltage (v fb1 > 1.3v), 2. intv cc undervoltage, 3. led overcurrent (v (isp-isn) > 375mv), or 4. thermal shutdown. if all faults are removed, fault flag returns high. fault status is only updated during pwm high state and latched during pwm low state. fault remains asserted until the ss pin is discharged below 0.2v for cases 2, 3 and 4 above. vmode (pin 16): an open-collector pull-down on vmode asserts if the fb1 input is above 1.19v (typical), and v (isp-isn) is less than 25mv (typical). to function, the pin requires an external pull-up resistor. vmode status is updated only during pwm high state and latched during pwm low state. sense (pin 18): the current sense input for the control loop. kelvin connect this pin to the positive terminal of the switch current sense resistor, r sense , in the source of the n-channel mosfet. the negative terminal of the current sense resistor should be kelvin connected to the gnd plane of the ic. gate (pin 19): n-channel mosfet gate driver output. switches between intv cc and gnd. it is driven to gnd during shutdown, fault or idle states. intv cc (pin 20): regulated supply for internal loads, gate driver and top gate (pmos) driver. supplied from v in and regulates to 7.7v (typical). intv cc must be bypassed with a 4.7f capacitor placed close to the pin. connect intv cc directly to v in if v in is always less than or equal to 7v. v in (pin 23): input supply pin. must be locally bypassed with a 0.22f (or larger) capacitor placed close to the ic. en/uvlo (pin 24): enable and undervoltage lockout pin. an accurate 1.22v falling threshold with externally programmable hysteresis detects when power is ok to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 3a pull-down current. above the threshold (but below 6v), en/uvlo input bias current is sub-a. below the falling threshold, a 3a pull-down current is enabled so the user can define the hysteresis with the external resistor selection. an undervoltage condition resets soft-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. v s (pin 25): current sense amplifier power supply pin. this pin supply current to the current sense amplifier and can operate from 3v to 100v. csn (pin 26): negative current sense input terminal. csn remains functional for voltages up to 100v. typically connected to v s and csp as shown in figure 9. csp (pin 27): positive current sense input terminal. the internal sense amplifier sinks current from csp to regulate it to the same potential as csn. a resistor (r in1 ) tied from v in to csp sets the output current i csout = v sns /r in1 . v sns is the voltage developed across r sns . see figure 9. csout (pin 28): current sense amplifier output. csout pin sources the current that is drawn from csp. typically is output to an external resistor to gnd.
lt3796 12 3796f block diagram lt3796 block diagram en/uvlo short-circuit detect fb1 v c ismon a1 a2 a3 1.22v 1.5v scilmb 2.5v v led gm eamp 3a 1.3v 0vfb comparator pwm comparator tgoffb 1.25v isp ovfb1 isp-7v shdn 1.25v isn 1.1v 100mv v s ? + ? + ? ? + ? + ? + 1.25v ctrl fb2 isp ss and fault logic ovfb1 ovfb2 scilmb tgoffb faultb intv cc ss thermal shdn pwm 10a at fb1 = 1.25v gm ? + tg x4 ? + a5 a6 gm a8 x1 +? 10a at a1 + = a1 ? 10a 1v 10a at fb2 = 1.25v 2.8a 1ma 28a csp 5.5v 5.5v csn + ? a11 csout 5.5v fault ss rt sync 3796 bd ? + a7 a9 ? + freq prog ? + + ramp generator 100khz to 1mhz oscillator pwm v in intv cc faultb driver i sense a9 ? + i lim 7.7v sense gnd gate ldo + ? a4 q r s 100a intv cc v ref ? + 1.19v fb1 2.015v a7 ? + 200mv v led c/10 comparator with 200mv hysteresis a7 ? + a13 a15 a12 a10 a9 a14 vmode 2.5v 113mv a16 1.3v 0vfb2 ? +
lt3796 13 3796f operation the lt3796 is a constant-frequency, current mode con - troller with a low side nmos gate driver. the operation of the lt3796 is best understood by referring to the block diagram. in normal operation, with the pwm pin low, the gate pin is driven to gnd, the tg pin is pulled high to isp to turn off the pmos disconnect switch, the v c pin goes high impedance to store the previous switching state on the external compensation capacitor, and the isp and isn pin bias currents are reduced to leakage levels. when the pwm pin transitions high, the tg pin transitions low after a short delay. at the same time, the internal oscillator wakes up and generates a pulse to set the pwm latch, turning on the external power n-channel mosfet switch (gate goes high). a voltage input proportional to the switch current, sensed by an external current sense resistor between the sense and gnd input pins, is added to a stabilizing slope compensation ramp and the resulting switch cur - rent sense signal is fed into the negative terminal of the pwm comparator. the current in the external inductor increases steadily during the time the switch is on. when the switch current sense voltage exceeds the output of the error amplifier, labeled v c , the latch is reset and the switch is turned off. during the switch off phase, the inductor current decreases. at the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. through this repetitive action, the pwm control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. the v c signal is integrated over many switching cycles and is an amplified version of the difference between the led current sense voltage, measured between isp and isn, and the target difference voltage set by the ctrl pin. in this manner, the error amplifier sets the correct peak switch current level to keep the led current in regulation. if the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. the switch current is monitored during the on phase and the voltage across the sense pin is not allowed to exceed the current limit threshold of 113mv (typical). if the sense pin exceeds the current limit threshold, the sr latch is reset regardless of the output state of the pwm comparator. likewise, any fault condition, i.e. fb1 overvoltage (v fb1 > 1.3v), led over current, or intv cc undervoltage (intv cc < 4v), the gate pin is pulled down to gnd immediately. in voltage feedback mode, the operation is similar to that described above, except the voltage at the v c pin is set by the amplified difference of the internal reference of 1.25v (nominal) and the fb1 and fb2 pins. if fb1 and fb2 are both lower than the reference voltage, the switch current increases; if fb1 or fb2 is higher than the refer - ence voltage, the switch demand current decreases. the led current sense feedback interacts with the voltage feedback so that neither fb1 or fb2 exceeds the internal reference and the voltage between isp and isn does not exceed the threshold set by the ctrl pin. for accurate current or voltage regulation, it is necessary to be sure that under normal operating conditions, the appropriate loop is dominant. to deactivate the voltage loop entirely, fb1 and fb2 can be connected to gnd. to deactivate the led current loop entirely, the isp and isn should be tied together and the ctrl input tied to v ref . two led specific functions featured on the lt3796 are controlled by the voltage feedback fb1 pin. first, when the fb1 pin exceeds a voltage 60mv lower (C5%) than the fb1 regulation voltage and v (isp-isn) is less than 25mv (typical), the pull-down driver on the vmode pin is activated. this function provides a status indicator that the load may be disconnected and the constant-voltage feedback loop is taking control of the switching regulator. when the fb1 pin exceeds the fb1 regulation voltage by 50mv (4% typical), the fault pin is activated. lt3796 features a pmos disconnect switch driver. the pmos disconnect switch can be used to improve the pwm dimming ratio, and operate as fault protection as well. once a fault condition is detected, the tg pin is pulled high to turnoff the pmos switch. the action isolates the led array from the power path, preventing excessive current from damaging the leds. a standalone current sense amplifier is integrated in the lt3796. it can work as input current limit or open led protection. the detailed information can be found in the application information section.
lt3796 14 3796f intv cc regulator bypassing and operation the intv cc pin requires a capacitor for stable operation and to store the charge for the large gate switching cur - rents. choose a 10v rated low esr, x7r or x5r ceramic capacitor for best performance. a 4.7f ceramic capacitor is adequate for many applications. place the capacitor close to the ic to minimize the trace length to the intv cc pin and also to the power ground. an internal current limit on the intv cc output protects the lt3796 from excessive on-chip power dissipation. the minimum value of this current limit should be considered when choosing the switching n-channel mosfet and the operating frequency. i intvcc can be calculated from the following equation: i intvcc = q g ? f osc careful choice of a lower q g mosfet allows higher switching frequencies, leading to smaller magnetics. the intv cc pin has its own undervoltage disable (uvlo) set to 4v (typical) to protect the external fets from excessive power dissipation caused by not being fully enhanced. if the intv cc pin drops below the uvlo threshold, the gate pin is forced to 0v, tg pin is pulled high and the soft-start pin will be reset. if the input voltage, v in , will not exceed 7v, then the intv cc pin should be connected to the input supply. be aware that a small current (typically 10a) loads the intv cc in shutdown. if v in is normally above, but occasionally drops below the intv cc regula- tion voltage, then the minimum operating v in is close to 6v. this value is determined by the dropout voltage of the linear regulator and the 4v intv cc undervoltage lockout threshold mentioned above. programming the turn-on and turn-off thresholds with the en/uvlo pin the falling uvlo value can be accurately set by the resistor divider. a small 3a pull-down current is active when en/ uvlo is below the threshold. the purpose of this current applications information is to allow the user to program the rising hysteresis. the following equations should be used to determine the values of the resistors: v in(falling) = 1.22 ? r1 + r2 r2 v in(rising) = v in(falling) + 3a ? r 1 led current programming the led current is programmed by placing an appropriate value current sense resistor r led between the isp and isn pins. typically, sensing of the current should be done at the top of the led string. if this option is not available, then the current may be sensed at the bottom of the string. the ctrl pin should be tied to a voltage higher than 1.2v to get the full-scale 250mv (typical) threshold across the sense resistor. the ctrl pin can also be used to dim the led current to zero, although relative accuracy decreases with the decreasing voltage sense threshold. when the ctrl pin voltage is less than 1v, the led current is: i led = v ctrl ? 100mv r led ? 4 , 0.1v < v ctrl 1v i led = 0, v ctrl = 0v when the ctrl pin voltage is between 1v and 1.2v, the led current varies with ctrl, but departs from the previ - ous equation by an increasing amount as the ctrl volt - age increases. ultimately above 1.2v, the led current no figure 1. lt3796 3796 f01 en/uvlo r1 r2 v in
lt3796 15 3796f longer varies with ctrl. the typical v (isp -isn) threshold vs ctrl is listed in the table 1. table 1. v (isp-isn) threshold vs ctrl v ctrl (v) v (isp-isn) (mv) 1 225 1.05 236 1.1 244.5 1.15 248.5 1.2 250 when ctrl is higher than 1.2v, the led current is regu - lated to: i led = 250mv r led the ctrl pin should not be left open (tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the led load, or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage signal (ripple) across isp and isn at the switching frequency is expected. the amplitude of this signal is increased by high led load current, low switching frequency and/or a smaller value output filter capacitor. programming output voltage (constant-voltage regulation) or open led/overvoltage threshold the lt3796 has two voltage feedback pins, fb1 and fb2. either one can be used for a boost or sepic application. the difference between these two pins is fb1 has a compara- tor that senses when fb1 exceeds v fb C 60mv ( vmode threshold) and asserts the vmode output if v (isp-isn) is less than 25mv. this indicates that the output is in voltage regulation mode and not current regulation. fb2 does not have this extra comparator. the output voltage can be set by selecting the values of r3 and r4 (see figure 2) ac - cording to the following equation: v out = 1.25 ? r3 + r4 r4 figure 2. feedback resistor connections for boost and sepic applications for a boost type led driver, set the resistor from the output to the fb1 pin such that the expected v fb1 during normal operation does not exceed 1.15v. for an led driver of buck mode or a buck-boost mode configuration, the fb voltage is typically level shifted to a signal with respect to gnd as illustrated in figure 3. the output can be expressed as: v out = 1.25 ? r5 r8 ? r6 + r7 r6 figure 3. feedback resistor connection for buck mode or buck-boost mode led driver applications information lt3796 3796 f02 fb1/fb2 r3 r4 v out lt3796 3796 f03 r8 r5 led string csp v out csn v s csout fb1 r led r6 r7 ? +
lt3796 16 3796f open led detection the lt3796 provides an open-collector status pin, vmode , that pulls low when the fb1 pin is above 1.19v and v (isp-isn) is less than 25mv. if the open led clamp volt - age is programmed correctly using the resistor divider, then the fb1 pin should never exceed 1.15v when leds are connected, therefore, the only way for the fb1 pin to be within 60mv of the 1.25v regulation voltage is for an open led event to have occurred. led over current protection feature the isp and isn pins have a short-circuit protection feature independent of the led current sense feature. this feature prevents the development of excessive switching currents and protects the power components. the short-circuit protection threshold (375mv, typ) is designed to be 50% higher than the default led current sense threshold. once the led over current is detected, the gate pin is driven to gnd to stop switching, and tg pin is pulled high to disconnect the led array from the power path. a typical led short-circuit protection scheme for boost or buck-boost mode converter is shown in figure 4. the schottky diode d2 should be put close to the drain of m2 on the board. it protects the led + node from swing- ing well below ground when being shorted to ground through a long cable. usually, the internal protection loop takes about 1s to respond. including pnp helper q1 is recommended to limit the transient short-circuit current. with the pnp helper, the short-circuit current can be limited to 2a, whereas the short-circuit current can reach to 20a without the pnp helper as shown in figure 5 and figure 6 respectively. refer to boost led driver with output short-circuit protection and led current monitor for the test schematic. note that the impedance of the short-circuit cable affects the peak current. applications information figure 4. the simplified led short-circuit protection schematic for boost/buck-boost mode led driver figure 5. short-circuit current without pnp helper figure 6. short-circuit current with pnp helper figure 7. the simplified led short-circuit protection schematic for buck mode converter i m2 10a/div fault 10v/div 3796 f05 1s/div led + 50v/div i m2 1a/div fault 10v/div 3796 f06 1s/div led + 50v/div lt3796 3796 f04 q1 r sns r led led + gnd (boost) or v in (buck-boost mode) led string d2 isp gate sense v in v in c1 m1 m2 isn tg c2 l1 d1 lt3796 3796 f07 led string tg isp isn v in v in r led r sns q1 d3 gate sense d1 d2 led + led ? l1 m1 m2 c2 c1
lt3796 17 3796f similar to boost, schottky diodes d2, d3 and pnp transis - tor q1 are recommended to protect short-circuit event in the buck mode. pwm dimming control for brightness there are two methods to control the led current for dim- ming using the lt3796. one method uses the ctrl pin to adjust the current regulated in the leds. a second method uses the pwm pin to modulate the led current between zero and full current to achieve a precisely programmed average current, without the possibility of color shift that occurs at low current in leds. to make pwm dimming more accurate, the switch demand current is stored on the v c node during the quiescent phase when pwm is low. this feature minimizes recovery time when the pwm signal goes high. to further improve the recovery time, a disconnect switch should be used in the led current path to prevent the output capacitor from discharging during the pwm signal low phase. the minimum pwm on or off time depends on the choice of operating frequency through the rt input. for best current accuracy, the minimum pwm high time should be at least three switching cycles (3s for f sw = 1mhz). a low duty cycle pwm signal can cause excessive start-up times if it were allowed to interrupt the soft-start sequence. therefore, once start-up is initiated by pwm > 1v, it will ignore a logical disable by the external pwm input signal. the device will continue to soft-start with switching and tg enabled until either the voltage at ss reaches the 1.0v level, or the output current reaches one-fourth of the full- scale current. at this point the device will begin following the dimming control as designated by pwm. if at any time an output overcurrent is detected, gate and tg will be disabled even as ss continues to charge. programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency from 100khz to 1mhz to optimize efficiency/performance or external component size. higher frequency operation yields smaller component size but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. lower frequency operation gives better performance at the cost of larger external component size. for an appropriate r t resistor value see table 2. an external resistor from the rt pin to gnd is requireddo not leave this pin open. table 2. typical switching frequency vs r t value (1% resistor) f osc (khz) r t (k) 1000 6.65 900 7.50 800 8.87 700 10.2 600 12.4 500 15.4 400 19.6 300 26.1 200 39.2 100 82.5 frequency synchronization the lt3796 switching frequency can be synchronized to an external clock using the sync pin. for proper operation, the r t resistor should be chosen for a switching frequency 20% lower than the external clock frequency. the sync pin is disabled during the soft-start period. observation of the following guidelines about the sync waveform will ensure proper operation of this feature. driving sync with a 50% duty cycle waveform is always a good choice, otherwise, maintain the duty cycle between 20% and 60%. when using both pwm and sync features, the pwm signal rising edge must have the aligned rising edges to achieve the optimized high pwm dimming ratio. if the sync pin is not used, it should be connected to gnd. duty cycle considerations switching duty cycle is a key variable defining converter operation, therefore, its limits must be considered when programming the switching frequency for a particular application. the fixed minimum on-time and minimum applications information
lt3796 18 3796f off-time (see figure 8) and the switching frequency define the minimum and maximum duty cycle of the switch, respectively. the following equations express the mini - mum/ maximum duty cycle: min duty cycle = minimum on-time ? switching frequency max duty cycle = 1 C minimum off-time ? switching frequency csn and csp pins. for boost and buck-boost applications, r in2(opt) and c opt are not required. applications information figure 9. setting input current limit figure 8. typical minimum on- and off-time vs temperature temperature (c) ?50 200 150 50 350 3796 f08 0?25 25 50 75 125100 150 100 0 250 300 time (ns) min on-time min off-time when calculating the operating limits, the typical values for on/off-time in the data sheet should be increased by at least 100ns to allow margin for pwm control latitude, gate rise/fall times and sw node rise/fall times. setting input current limit the lt3796 has a standalone current sense amplifier. it can be used to limit the input current. as shown in figure 9, the input current signal is converted to voltage output at csout pin. when the csout voltage exceeds fb2 regula - tion voltage, the gate is pulled low, and the converter stops switching. the input current limit is calculated as follows: i in = 1.25 ? r in1 r out ? r sns for buck applications, filter components, r in2(opt) and c opt , are recommended to be placed close to lt3796 to suppress the substantial transient signal or noise at across thermal considerations the lt3796 is rated to a maximum input voltage of 100v. careful attention must be paid to the internal power dis - sipation of the ic at higher input voltages to ensure that a junction temperature of 150c is not exceeded. this junction limit is especially important when operating at high ambient temperatures. the majority of the power dis - sipation in the ic comes from the supply current needed to drive the gate capacitance of the external power n-channel mosfet. this gate drive current can be calculated as: i gate = f sw ? q g a low q g power mosfet should always be used when operating at high input voltages, and the switching fre - quency should also be chosen carefully to ensure that the ic does not exceed a safe junction temperature. the internal junction temperature, t j of the ic can be estimated by: t j = t a + [v in ? (i q + f sw ? q g ) ? ja ] where t a is the ambient temperature, i q is the v in operating current of the part (2.5ma typical) and ja is the package thermal impedance (30c/w for the tssop package). for example, an application with t a(max) = 85c, v in(max) = 60v, f sw = 400khz, and having a n-channel mosfet with lt3796 3796 f03 r in2(opt) r sns r in1 csp fb2 csn to load v in i in v s csout v s c opt ? + r out c filt +v sns ?
lt3796 19 3796f q g = 20nc, the maximum ic junction temperature will be approximately: t j = 85c + [60v ? (2.5ma + 400khz ? 20nc) ? 30c/w] 104c the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the ic. it is best if the copper plane is extended on either the top or bottom layer of the pcb to have the maximum exposure to air. internal ground layers do not dissipate thermals as much as top and bottom layer copper does. see recom - mended layout as an example. input capacitor selection the input capacitor supplies the transient input current for the power inductor of the converter and must be placed and sized according to the transient current requirements. the switching frequency, output current and tolerable input voltage ripple are key inputs to estimating the capacitor value. an x7r type ceramic capacitor is usually the best choice since it has the least variation with temperature and dc bias. typically, boost and sepic converters re - quire a lower value capacitor than a buck mode converter. assuming that a 100mv input voltage ripple is acceptable, the required capacitor value for a boost converter can be estimated as follows (t sw = 1/f osc ): c in (f) = i led (a) ? v led v in ? t sw (s) ? 1f a ? s ? 2.8 therefore, a 2.2f capacitor is an appropriate selection for a 400khz boost regulator with 12v input, 48v output and 500ma load. with the same v in voltage ripple of less than 100mv, the input capacitor for a buck converter can be estimated as follows: c in (f) = i led (a) ? v led (v in ? v led ) v in 2 ? t sw (s) ? 10f a ? s a 10f input capacitor is an appropriate selection for a 400khz buck mode converter with 24v input, 12v output and 1a load. in the buck mode configuration, the input capacitor has large pulsed currents due to the current returned through the schottky diode when the switch is off. it is important to place the capacitor as close as possible to the schottky diode and to the gnd return of the switch (i.e., the sense resistor). it is also important to consider the ripple current rating of the capacitor. for best reliability, this capacitor should have low esr and esl and have an adequate ripple current rating. the rms input current for a buck mode led driver is: i in(rms) = i led ? (1Cd)d d = v led v in where d is the switch duty cycle. table 3. recommended ceramic capacitor manufacturers manufacturer web tdk www.tdk.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com avx www.avx.com output capacitor selection the selection of the output capacitor depends on the load and converter configuration, i.e., step-up or step-down and the operating frequency. for led applications, the equivalent resistance of the led is typically low and the output filter capacitor should be sized to attenuate the current ripple. use of an x7r type ceramic capacitor is recommended. to achieve the same led ripple current, the required filter capacitor is larger in the boost and buck-boost mode ap - plications than that in the buck mode applications. lower operating frequencies will require proportionately higher capacitor values. applications information
lt3796 20 3796f power mosfet selection for applications operating at high input or output voltages, the power n-channel mosfet switch is typically chosen for drain voltage v ds rating and low gate charge q g . consideration of switch on-resistance, r ds(on) , is usually secondary because switching losses dominate power loss. the intv cc regulator on the lt3796 has a fixed current limit to protect the ic from excessive power dissipation at high v in , so the mosfet should be chosen so that the product of q g at 7.7v and switching frequency does not exceed the intv cc current limit. for driving leds be careful to choose a switch with a v ds rating that exceeds the threshold set by the fb pin in case of an open load fault. several mosfet vendors are listed in table 4. the mosfets used in the application circuits in this data sheet have been found to work well with the lt3796. consult factory applications for other recommended mosfets. table 4. mosfet manufacturers vendor web vishay siliconix www.vishay.com fairchild www.fairchildsemi.com international rectifier www.irf.com infineon www.infineon.com high side pmos disconnect switch selection a high side pmos disconnect switch with a minimum v th of C1v to C2v is recommended in most lt3796 ap - plications to optimize or maximize the pwm dimming ratio and protect the led string from excessive heating during fault conditions as well. the pmos disconnect switch is typically selected for drain-source voltage v ds , and continuous drain current i d . for proper operations, v ds rating must exceed the open led regulation voltage set by the fb1 pin, and i d rating should be above i led . schottky rectifier selection the power schottky diode conducts current during the interval when the switch is turned off. select a diode rated for the maximum sw voltage. if using the pwm feature for dimming, it is important to consider diode leakage, which increases with the temperature, from the output during the pwm low interval. therefore, choose the schottky diode with sufficiently low leakage current. table 5 has some recommended component vendors. table 5. schottky rectifier manufacturers vendor web on semiconductor www.onsemi.com diodes, inc www.diodes.com central semiconductor www.centralsemi.com rohm semiconductor www.rohm.com sense resistor selection the resistor, r sense , between the source of the external n-channel mosfet and gnd should be selected to provide adequate switch current to drive the application without exceeding the 113mv (typical) current limit threshold on the sense pin of lt3796. for buck mode applications, select a resistor that gives a switch current at least 30% greater than the required led current. for buck mode, select a resistor according to: r sense(buck) 0.07v i led for buck-boost mode, select a resistor according to: r sense(buck ? boost ) v in ? 0.07v (v in + v led )i led for boost, select a resistor according to: r sense(boost ) v in ? 0.07v v led ? i led the placement of r sense should be close to the source of the nmos fet and gnd of the lt3796. the sense input to lt3796 should be a kelvin connection to the positive terminal of r sense . 70mv is used in the equations above to give some margin below the 113mv (typical) sense current limit threshold. applications information
lt3796 21 3796f applications information inductor selection the inductor used with the lt3796 should have a saturation current rating appropriate to the maximum switch current selected with the r sense resistor. choose an inductor value based on operating frequency, input and output voltage to provide a current mode signal on sense of approximately 20mv magnitude. the following equations are useful to estimate the inductor value (t sw = 1/f osc ): l buck = t sw ? r sense ? v led (v in ? v led ) v in ? 0.02v l buck, boost = t sw ? r sense ? v led ? v in (v led + v in ) ? 0.02v l boost = t sw ? r sense ? v in (v led ? v in ) v led ? 0.02v table 6 provides some recommended inductor vendors. table 6. inductor manufacturers vendor web sumida www.sumida.com wrth elektronik www.we-online.com coiltronics www.cooperet.com vishay www.vishay.com coilcraft www.coilcraft.com loop compensation the lt3796 uses an internal transconductance error amplifier whose v c output compensates the control loop. the external inductor, output capacitor and the compen - sation resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on performance, size and cost. the compensation resistor and capacitor at v c are selected to optimize control loop response and stability. for typical led applications, a 22nf compensation capacitor at v c is adequate, and a series resistor should always be used to increase the slew rate on the v c pin to maintain tighter regulation of led current during fast transients on the input supply to the converter. soft-start capacitor selection for many applications, it is important to minimize the inrush current at start-up. the built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 2v 28 a a typical value for the soft-start capacitor is 0.1f. the soft-start pin reduces the oscillator frequency and the maximum current in the switch. soft-start also operates as fault protection, which forces the converter into hiccup or latchoff mode. detailed information is provided in the fault protection: hiccup mode and latchoff mode section. fault protection: hiccup mode and latchoff mode if an led overcurrent condition, intv cc undervoltage, or thermal limit happens, an open-drain pull-down on fault asserts. the tg pin is pulled high to disconnect the led array from the power path, and the gate pin is driven low. if the soft-start pin is charging and still below 1.7v, then it will continue to do so with a 28a source. once above 1.7v, the pull-up source is disabled and a 2.8a pull-down is activated. while the ss pin is discharging, the gate is forced low. when ss pin is discharged below 0.2v, a new cycle is initiated. this is referred as hiccup mode operation. if the fault still exists when ss crosses below 0.2v, then a full ss charge/discharge cycle has to complete before switching is enabled and the fault flag is deasserted. if a resistor is placed between v ref pin and ss pin to hold ss pin higher than 0.2v during a fault, then the lt3796 will enter latchoff mode with gate pin low, tg pin high and fault pin low. to exit latchoff mode, the en/uvlo pin must be toggled low to high.
lt3796 22 3796f board layout the high speed operation of the lt3796 demands careful attention to board layout and component placement. the exposed pad of the package is the gnd terminal of the ic and is also important for thermal management of the ic. it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. to reduce electromagnetic interference (emi), it is important to minimize the area of the high dv/dt switching node between the inductor, switch drain and anode of the schottky rectifier. use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. the lengths of the high di/dt traces: 1) from the switch node through the switch and sense resistor to gnd, and 2) from the switch node through the schottky rectifier and filter capacitor to gnd should be minimized. the ground points of these two switching current traces should come to a common point then connect to the ground plane under the lt3796. likewise, the ground terminal of the bypass capacitor for the intv cc regulator should be placed near the gnd of the switching path. typically, this requirement results in the external switch being closest to the ic, along with the intv cc bypass capacitor. the ground for the compensation network and other dc control signals should be star connected to the underside of the ic. do not extensively route high impedance signals such as fb1, fb2, rt and v c , as they may pick up switching noise. since there is a small variable dc input bias current to the isn and isp inputs, resistance in series with these pins should be minimized to avoid creating an offset in the current sense threshold. likewise, minimize resistance in series with the sense input to avoid changes (most likely reduction) to the switch current limit threshold. figure 10 is a suggested two sided layout for a boost converter. note that the 4-layer layout is recommended for best performance. please contact the factory for the reference layout design. applications information
lt3796 23 3796f applications information figure 10. boost converter suggested layout 3796 f10 lt3796 2 3 1 4 5 6 7 8 9 10 11 12 13 14 21 20 22 19 18 17 16 15 26 27 28 23 24 25 m2 led + x out via via from isp via from v in via from v in via from isn ismon via from intv cc via from gate sync pwm via from tg x x x x 29 x x x x x x isp via isn via tg via component designations refer to boost led driver with output short circuit protection and led current monitor q1 m1 v in via x c3 r sns1 r sns r4 r3 r9 r10 r6 r5 r8 r7 c c r c r2 c6 r t via from out via from v in c2 c2 c2 c2 c5 l1 d1 2 3 1 4 6 7 8 5 6 7 5 8 2 3 4 1 r led d2 r1 v in v ref vias to ground plane x x routing on the 2nd layer c1 c1 c1 x x x x intv cc via gate via c4
lt3796 24 3796f typical applications boost led driver with output short circuit protection and led current monitor fault (short led) protection without r11: hiccup mode fault (short led) protection with r11: latchoff mode i m2 1a/div fault 10v/div 3796 ta02b 50ms/div ss 2v/div led + 50v/div i m2 1a/div fault 10v/div 3796 ta02c 50ms/div led + 50v/div ss 2v/div r2 118k cspv s v in csn ss v ref r5 2k 85v led lt3796 3796 ta02a ctrl csout pwm sync pwm sync m1: infineon bcs160n10ns3-g m2: vishay siliconix si7113dn l1: coiltronics dr127-220 d1: diodes inc pds5100 d2: vishay es1c q1: zetex fmmt589 led: cree xlamp xr-e ismon en/uvlo gnd fb1 isp isn tg gate sense l1 22h r sns1 50m i in 9v to 60v 100v (transient) d1 r c 10k r t 31.6k 250khz c c 10nf r3 499k r4 97.6k r1 1m c1 2.2f 3 v in c2 2.2f 4 100v r8 13.7k r sns 15m r led 620m m2 q1 m1 d2 up to 400ma r6 40.2k c3 10nf c sout optional input current reporting r7 1m vmode fault vmode fault led current reporting r11 optional for fault latchoff r11 402k (opt) v c rt fb2 intv cc c5 4.7f c6 0.1f intv cc r10 100k r9 100k intv cc c4 0.1f
lt3796 25 3796f typical applications buck led driver with open led flag and led current reporting efficiency vs v in v in (v) 20 75 100 3796 ta03b 30 40 50 7060 80 80 70 85 95 90 efficiency (%) r2 61.9k ispv s v in tgisn rt ss v c sync m1 lt3796 3796 ta03a ctrl pwm fb2 ismon pwm led current reporting en/uvlo v ref csout fb1 gate sense gnd intv cc csp csn c c 4.7nf r1 1m l1 33h r led 100m m2 led + 24v to 80v d1 2.5a r t 19.6k 400khz r c 10k c3 4.7f intv cc c4 0.1f c5 0.1f v in c2 4.7f 2 25v r6 59k r3 49.9k r4 49.9k r5 1m r sns 15m 18v led c1 2.2f 3 100v m1: vishay siliconix si7454dp m2: vishay siliconix si7113dn d1: diodes inc pds3100 l1: coiltronics hc9-220 led: cree xlamp xm-l vmode fault vmode fault r8 100k r9 100k intv cc
lt3796 26 3796f sepic led driver using fb2 for input overvoltage protection typical applications v in (v) 0 75 100 3796 ta04b 10 20 30 5040 60 80 70 85 95 90 efficiency (%) efficiency vs v in cspv s csn rt sync ss v c vmode fault r6 2k 22v led lt3796 3796 ta04a ctrl fb2 csout pwm pwm optional input current reporting m1: vishay siliconix si7456dp m2: zetex zxmp6a13f l1: coiltronics drq127-330 d1: diodes inc pds5100 led: cree xlamp xr-e ismon led current reporting en/uvlo v ref gnd fb1 isp isn tg intv cc intv cc gate sense c c 10nf l1a 33h r sns1 50m i in d1 r t 19.6k 400khz r c 4.99k v in c5 4.7f c4 0.1f c7 0.1f r4 511k r5 100k 8v to 60v v in c2 10f 3 25v c1 2.2f 3 100v r11 40.2k r sns 15m r led 250m up to 1a m2 m1 l1b r7 40.2k c3 0.1f c sout r10 909k c6 2.2f 100v r3 20k r2 75k ? ? r1 953k vmode fault r8 100k r9 100k intv cc
lt3796 27 3796f sepic sealed lead acid (sla) battery charger typical applications v charge , v float vs temperature temperature (c) 17.5 3796 ta05b ?40 ?30 ?20 0 10 20 30 40 ?10 80 50 60 70 13.0 14.0 14.5 15.0 15.5 16.0 16.5 17.0 12.5 13.5 v charge , v float (v) v charge v float r3 20k cspv s v in csn rt v c fault r6 2k lt3796 3796 ta05a ctrl fb2 csout pwm tg sync v ref output current reporting optional input current reporting m1: vishay siliconix si7456dp m2: vishay sud19p06-60-e3 m3: zetex zxm61n03f l1: coilcraft msd1260-333 d1: on semi mbrs260t3g d2: central semi cmdz15l r11: murata ncp18xh103f03rb ismon ss en/uvlo v ref fb1 isp isn vmode vmode fault out bat intv cc intv cc gate sense gnd c c 10nf l1a 33h r sns1 50m m2 i in 8v to 40v 100v (transient) d1 r sns2 250m r t 19.6k 400khz r c 499 c4 0.1f r4 357k r5 100k r2 806k r1 10k d2 15v c1 4.7f 50v v in bat r13 93.1k r sns 15m m3 m1 r7 40.2k c3 10nf c sout r12 30.1k r11 10k ntc r10 10.2k ? c5 4.7f r7 49.9k r12 49.9k l1b c6 2.2f 100v out v charge = 14.6v v float = 13.5v at 25c ? bat c2 10f + r9 113k c7 0.1f
lt3796 28 3796f 28v in to 28v supercap charger with input current limit and charge done flag typical applications input and output current vs output voltage v out (v) 0 800 600 200 1800 3796 ta06b 5 10 15 25 i out 20 30 400 0 1000 1600 1400 1200 input/output current (ma) i in cspv s v in csn ctrl rt v c v ref r1 20k lt3796 3796 ta06a pwm sync csout fb2 v ref output current reporting l1: coilcraft msd1260-333 d1: on semi mbrs260t3g m1: vishay siliconix si7850 q1: zetex fmmt591a ss en/uvlo ismon gnd fb1 isp isn tg intv cc gate sense l1a 33h l1b r sns1 150m 1.33a max v out = 0v to 28v 28v d1 c c 22nf r c 499 r t 19.6k 400khz c6 4.7f c4 0.1f c1 10f v in c2 4.7f 2 50v c6 10f r9 24.9k r sns 33m r sns2 150m supercap m1 1.67a max r2 124k r5 1m r3 499k r10 499k v out r4 30.1k q1 c3 0.1f c sout c7 0.1f r8 536k c5 0.1f ? ? input current reporting and limit chgdone fault vmode fault r7 100k r6 100k intv cc
lt3796 29 3796f typical applications sepic converter with r wire compensation and output current limit line impedance compensation i load (ma) 13.0 3796 ta08b 0 400 600 800 1000 1200 200 11.0 10.5 10.0 11.5 12.5 12.0 v out /v load (v) v out v load r wire = 0.5 load step response v out 500mv/div (ac) 3796 ta08c 500s/div i out 500ma/div 200ma 800ma gate gnd v in sense rt v c lt3796 3796 ta08a pwm sync fb2 v ref l1: wrth 744871220 d1: zetex zlls2000ta m1: vishay siliconix si4840dy ss ctrl v ref en/uvlo ismon csn out v s csp csout fb1 tg intv cc intv cc isp isn l1a 22h l1b m1 c2 10f out r wire v load 12v, 1a current limit r sns1 250m 12v d1 1:1 c c 10nf r t 19.6k 400khz r c 24.9k c6 4.7f c5 0.1f c8 0.1f c1 10f v in c3 10f c4 100f 25v ? r sns 33m c7 1f ? r1 38.3k r2 38.3k r3 154k r4 287k r5 12.4k + vmode fault vmode fault r7 100k r6 100k intv cc
lt3796 30 3796f typical applications solar panel driven sla battery charger with maximum power point tracking i charge vs v in v in (v) 1.2 3796 ta09b 20 30 35 40 25 0.4 0.2 0 0.6 0.8 1.0 i charge (a) csn v in v s csp rt v c fault lt3796 3796 ta09a ctrl csout fb2 pwm tg m1: vishay siliconix si7456dp m2: vishay sud19p06-60-e3 m3: zetex zxm61n03f l1: coilcraft msd1260-333 d1: on semi mbrs260t3g d2: central semi cmdz15l r9: murata ncp18xh103f03rb v ref ismon sync ss en/uvlo fb1 out isp isn intv cc intv cc fault gate sense gnd l1a 33h out r sns1 250m r10 30.1k l1b wrth solar panel v oc = 37.5v v mpp = 28v d1 1:1 r t 19.6k 400khz r c 499 c c 22nf c4 0.1f c3 0.1f c sout c1 4.7f 50v v in bat c2 10f bat v charge = 14.6v v float = 13.5v at 25c bat r9 10k ntc ? r5 137k intv cc r4 301k + r11 93.1k r sns 15m m1 m3 r12 10.2k r8 113k r3 20k r2 475k m2 d2 15v r6 100k r1 10k c6 2.2f 100v ? c6 0.1f vmode vmode r7 49.9k r12 49.9k c5 4.7f
lt3796 31 3796f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe28 (eb) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation eb fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation eb please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3796 32 3796f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0412 ? printed in usa related parts typical application part number description comments lt3791 60v, synchronous buck-boost 1mhz led controller v in : 4.7v to 60v, v out range: 0v to 60v, true color pwm, analog = 100:1, i sd < 1a, tssop-38e package lt3755/lt3755-1 lt3755-2 high side 60v, 1mhz led controller with true color 3,000:1 pwm dimming v in : 4.5v to 40v, v out range: 5v to 60v, true color pwm, analog = 3000:1, i sd < 1a, 3mm 3mm qfn-16, msop-16e packages lt3756/lt3756-1 lt3756-2 high side 100v, 1mhz led controller with true color 3,000:1 pwm dimming v in : 6v to 100v, v out range: 5v to 100v, true color pwm, analog = 3000:1, i sd < 1a, 3mm 3mm qfn-16, msop-16e packages LT3743 synchronous step-down 20a led driver with three-state led current control v in : 5.5v to 36v, v out range: 5.5v to 35v, true color pwm, analog = 3000:1, i sd < 1a, 4mm 5mm qfn-28, tssop-28e packages ltc3780 high efficiency, synchronous, 4-switch buck-boost controller v in : 4v to 36v, v out range: 0.8v to 30v, i sd < 55a, ssop-24, qfn-32 packages ltc3789 high efficiency, synchronous, 4-switch buck-boost controller v in : 4v to 38v, v out range: 0.8v to 38v, i sd < 40a, 4mm 5mm qfn-28, ssop-28 packages lt3517 1.3a, 2.5mhz high current led driver with 3,000:1 dimming v in : 3v to 30v, true color pwm, analog = 3000:1, i sd < 1a, 4mm 4mm qfn-16 package lt3518 2.3a, 2.5mhz high current led driver with 3,000:1 dimming v in : 3v to 30v, true color pwm, analog = 3000:1, i sd < 1a, 4mm 4mm qfn-16 package lt3474/lt3474-1 36v, 1a (iled), 2mhz, step-down led driver v in : 4v to 36v, v out range = 13.5v, true color pwm = 400:1, i sd < 1a, tssop-16e package lt3475/lt3475-1 dual 1.5a(iled), 36v, 2mhz, step-down led driver v in : 4v to 36v, v out range = 13.5v, true color pwm, analog = 3000:1, i sd < 1a, tssop-20e package buck-boost mode led driver with open led clamp and output voltage limit efficiency vs v in v in (v) 100 3796 ta07b 0 20 30 40 50 60 10 80 75 70 85 90 95 efficiency (%) pwm = v ref csp v s v in csn rt v c ss sync 25v led 250ma lt3796 3796 ta07a v ref csout fb1 pwm pwm led current reporting ismon en/uvlo ctrl gnd fb2 isp isn tg intv cc intv cc gate sense c c 10nf l1 68h d1 r t 19.6k 400khz r c 4.99k c5 4.7f c6 0.1f c4 0.1f r1 1m r2 187k r6 200k r5 20k r4 715k c1 2.2f 2 9v to 55v 75v (transient) v in c3 4.7f 2 v in r8 13.3k r sns 33m r led 1 m2 v in m1 r3 249k r7 1m c2 1f vmode fault m1: fairchild semiconductor fdm3622 m2: zetex zxmp6a13f l1: wrth 744066680 d1: irf 10bq100 led: cree xlamp xr-e vmode fault r10 100k r9 100k intv cc

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